1. Field of the Invention
The invention relates to computer systems and more particularly to a computer system having a high speed communication link with multiple channels operating on he communication link.
2. Description of the Related Art
Traditional personal computer architectures partition the computer system into the various blocks shown in the exemplary prior art system illustrated in FIG. 1. One central feature of this prior art architecture is the use of the Peripheral Component Interface (PCI) bus 101 as the connection between the xe2x80x9cnorth bridgexe2x80x9d integrated circuit 103 and the xe2x80x9csouth bridgexe2x80x9d integrated circuit 105. The north bridge functions generally as a switch connecting CPU 107, a graphics bus 109 such as the Advanced Graphics Port (AGP) bus, the PCI bus and main memory 111. The north bridge also contains the memory controller function.
The south bridge generally provides the interface to the input/output (I/O) portion of the system with the possible exception of video output as illustrated in FIG. 1. Specifically, the south bridge 105 provides a bridge between the PCI bus and legacy PC-AT (Advanced Technology) logic. The south bridge also provides a bridge to the legacy ISA bus 115, the Integrated Device Electronics (IDE) disk interface 117 and the Universal Serial Bus (USB) 119. In the illustrated prior art architecture, PCI bus 101 also functions as the major input/output bus for add-in functions such as network connection 121. The various busses and devices shown in FIG. 1 are conventional in the personal computer industry and are not described further herein unless necessary for an understanding of the present invention.
In current and future personal computer systems, two basic types of data are transferred between integrated circuits: isochronous data and asynchronous data. Isochronous data refers to data used in real-time data streams such as audio data or motion-picture video data. Asynchronous data is used for all other transfers, such as central processing unit (CPU) accesses to memory and peripherals or bulk data transmissions from a hard drive into system memory.
The PCI bus causes a lack of determinism in the system because any function on the PCI bus can become master of the bus and tie up the bus. Thus, the throughput available on the PCI bus for a particular transfer and the latency that is involved for that transfer is unknown. PCI bus load fluctuations can result in uncertain and irregular quality of service. Therefore, having a PCI bus as the major input/output bus means that the major input/output bus of present day computer systems does not provide proper support for both isochronous and asynchronous data. If a computer system gives asynchronous data priority or treats isochronous data as asynchronous data, then those functions relying on real time data, such as motion-picture video, may not function satisfactorily. Alternatively, if a computer system prioritizes isochronous data, then the performance of the computer system can suffer since the latency of asynchronous data may become unacceptably long. As computer systems are called on to perform more and more real time activity, such as real time video, it becomes more critical that asynchronous and isochronous data be treated in a manner that prevents problems from occurring in the real time tasks without adversely effecting other aspects of computer performance.
In addition, as the number of functions integrated onto the integrated circuits of computer systems increases, the need for additional integrated circuit package pins also increases. Supporting the host bus, the memory interface, the PCI bus and a graphics interface results in a north bridge integrated circuit having a relatively large number of pins that is relatively unpopulated in terms of the number of transistors on the integrated circuit. The large number of pins requires the integrated circuit to be larger than would otherwise be necessary and therefore increases costs.
It would be desirable therefore, to have a deterministic high speed major interconnect bus providing improved quality of service for both isochronous and asynchronous traffic classes. It would also be desirable to reduce the pressure for additional pins on the integrated circuits making up the computer system.
Accordingly, a communication link is provided that carries transactions between functions over multiple logical pipes. Various logical pipe structures are possible. In one embodiment of the invention an integrated circuit includes a first function and a target concentrator circuit coupled to the first function. In one implementation, the target concentrator has multiple pipes from multiple functions coupled to a single target function and thus is a circuit that terminates multiple pipes. A receiver circuit, coupled to the communication link, receives transactions carried over the plurality of logical pipes on the communication link. Each pipe is uniquely identified by a pipe identification. The receiver circuit includes a router circuit, that routs transactions having any one of the pipe identifications of those pipes coupled to respective ones of the multiple functions, to the target concentrator circuit.
In another embodiment of the invention a method is provided for communicating in a computer system having a first integrated circuit that includes a first function, a transmit and a receive circuit coupled to an interconnect bus and a target concentrator circuit coupled between the first function and the transmit and receive circuits. The method includes receiving a communication into the receive circuit from one of a plurality of other functions coupled through associated logical pipes on the interconnect bus and routing the communication to the target concentrator circuit when any one of a plurality of pipe identifications corresponding to the associated logical pipes is contained in the communication. The information is carried on the pipes on a packet multiplexed basis.